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Espressif Systems /ESP32-H2 /MCPWM0 /TASK_EN

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Interpret as TASK_EN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TASK_CMPR0_A_UP_EN)TASK_CMPR0_A_UP_EN 0 (TASK_CMPR1_A_UP_EN)TASK_CMPR1_A_UP_EN 0 (TASK_CMPR2_A_UP_EN)TASK_CMPR2_A_UP_EN 0 (TASK_CMPR0_B_UP_EN)TASK_CMPR0_B_UP_EN 0 (TASK_CMPR1_B_UP_EN)TASK_CMPR1_B_UP_EN 0 (TASK_CMPR2_B_UP_EN)TASK_CMPR2_B_UP_EN 0 (TASK_GEN_STOP_EN)TASK_GEN_STOP_EN 0 (TASK_TIMER0_SYNC_EN)TASK_TIMER0_SYNC_EN 0 (TASK_TIMER1_SYNC_EN)TASK_TIMER1_SYNC_EN 0 (TASK_TIMER2_SYNC_EN)TASK_TIMER2_SYNC_EN 0 (TASK_TIMER0_PERIOD_UP_EN)TASK_TIMER0_PERIOD_UP_EN 0 (TASK_TIMER1_PERIOD_UP_EN)TASK_TIMER1_PERIOD_UP_EN 0 (TASK_TIMER2_PERIOD_UP_EN)TASK_TIMER2_PERIOD_UP_EN 0 (TASK_TZ0_OST_EN)TASK_TZ0_OST_EN 0 (TASK_TZ1_OST_EN)TASK_TZ1_OST_EN 0 (TASK_TZ2_OST_EN)TASK_TZ2_OST_EN 0 (TASK_CLR0_OST_EN)TASK_CLR0_OST_EN 0 (TASK_CLR1_OST_EN)TASK_CLR1_OST_EN 0 (TASK_CLR2_OST_EN)TASK_CLR2_OST_EN 0 (TASK_CAP0_EN)TASK_CAP0_EN 0 (TASK_CAP1_EN)TASK_CAP1_EN 0 (TASK_CAP2_EN)TASK_CAP2_EN

Description

MCPWM task enable register

Fields

TASK_CMPR0_A_UP_EN

set this bit high to enable PWM generator0 timer stamp A’s shadow register update task receive
TASK_CMPR1_A_UP_EN

set this bit high to enable PWM generator1 timer stamp A’s shadow register update task receive
TASK_CMPR2_A_UP_EN

set this bit high to enable PWM generator2 timer stamp A’s shadow register update task receive
TASK_CMPR0_B_UP_EN

set this bit high to enable PWM generator0 timer stamp B’s shadow register update task receive
TASK_CMPR1_B_UP_EN

set this bit high to enable PWM generator1 timer stamp B’s shadow register update task receive
TASK_CMPR2_B_UP_EN

set this bit high to enable PWM generator2 timer stamp B’s shadow register update task receive
TASK_GEN_STOP_EN

set this bit high to enable all PWM generate stop task receive
TASK_TIMER0_SYNC_EN

set this bit high to enable timer0 sync task receive
TASK_TIMER1_SYNC_EN

set this bit high to enable timer1 sync task receive
TASK_TIMER2_SYNC_EN

set this bit high to enable timer2 sync task receive
TASK_TIMER0_PERIOD_UP_EN

set this bit high to enable timer0 period update task receive
TASK_TIMER1_PERIOD_UP_EN

set this bit high to enable timer1 period update task receive
TASK_TIMER2_PERIOD_UP_EN

set this bit high to enable timer2 period update task receive
TASK_TZ0_OST_EN

set this bit high to enable one shot trip0 task receive
TASK_TZ1_OST_EN

set this bit high to enable one shot trip1 task receive
TASK_TZ2_OST_EN

set this bit high to enable one shot trip2 task receive
TASK_CLR0_OST_EN

set this bit high to enable one shot trip0 clear task receive
TASK_CLR1_OST_EN

set this bit high to enable one shot trip1 clear task receive
TASK_CLR2_OST_EN

set this bit high to enable one shot trip2 clear task receive
TASK_CAP0_EN

set this bit high to enable capture0 task receive
TASK_CAP1_EN

set this bit high to enable capture1 task receive
TASK_CAP2_EN

set this bit high to enable capture2 task receive

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data